1. Field of the Invention
The present invention relates to a memory testing apparatus for testing a non-volatile memory from which the stored data call be electrically erased ill all bits en bloc or in block by block en bloc and in which data can be rewritten, the non-volatile memory being called, for example, a flash memory, a flash EEPROM or flash E2PROM (flash electrically erasable programmable read only memory), or the like.
2. Description of the Related Art
Among PROMs (programmable read only memories) which are rewritable read only memories is called xe2x80x9cflash memoryxe2x80x9d in this technical field a memory the stored contents of which is replaceable by electrically erasing the stored contents in all bits en bloc or in block by block en bloc and rewriting data therein. As shown in FIG. 8, the inside of this flash memory (for example, NAND type flash memory) is separated into a plurality of blocks (in this example, 1024 blocks of No. 1 to No. 1024). Each of the blocks is constituted by N pages (N is an integer equal to or greater than 2), and each of the N pages is constituted by M bits (M is an integer equal to or greater than 2). Such flash memory is constructed such that the stored contents thereof can be electrically erased not only in all bits en bloc but also in block by block en bloc, and the stored contents thereof can be replaced by rewriting data in one block or in all blocks the stored contents of each of which have. been erased. In general, there are many cases that each block comprises 16 pages (N=16) and each page comprises 512 bits (M=512).
Conventionally, this flash memory is tested and measured by a memory testing apparatus for testing and measuring a commonplace memory (for example, a memory constituted by a semiconductor integrated circuit (IC)). FIG. 9 shows a configuration of a ordinary memory testing apparatus that has conventionally been used.
The illustrated memory testing apparatus comprises a main controller 100, a testing apparatus proper 200.called xe2x80x9cmain framexe2x80x9d in this technical field and a test head 300. The testing apparatus proper 200 comprises, in this example, a timing generator TG, a pattern generator PG, a waveform formatter FC, drivers DR, a voltage comparator VCP, a logical comparator LOC and a failure analysis memory AFM.
The test head 300 is constructed separately from the testing apparatus proper 200, and a predetermined number of device sockets (not shown) are usually mounted on the top portion of the test head 300. In addition, a printed board called xe2x80x9cpin cardxe2x80x9d in this technical field is accommodated within the test head 300, and a circuit containing the drivers DR and the voltage comparator VCP of the testing apparatus proper 200 is usually formed on this pin card. In general, the test head 300 is mounted to a test section of a semiconductor device transporting and handling apparatus called xe2x80x9chandlerxe2x80x9d in this technical field, and the test head 300 is electrically connected to the testing apparatus proper 200 by signal transmission means such as cables, optical fibers or the like.
A memory to be tested (a memory under test) MUT is mounted on a device socket of the test head 300, through which a test pattern signal is written in the memory under test MUT from the testing apparatus proper 200 and a response signal read out of the memory under test MUT is supplied to the testing apparatus proper 200, thereby to perform the test and the measurement for the memory under test MUT.
Further, in FIG. 9 only the drivers DR are shown in the plural form (four in this example), but, in reality, there are provided a predetermined number of drivers DR, for example 512 drivers. In addition, in FIG. 9, in order to simplify the drawing, each of the components in the main frame 200 (the timing generator TG, the pattern generator PG, the waveform formatter FC, the voltage comparator VCP, the logical comparator LOC and the failure analysis memory AFM) except the drivers DR is shown as one block, but in practice the remaining components in the main frame 200 except the timing generator TG are also provided by the same number (512) as that of the drivers DR, respectively. That is, only the timing generator TG is used in common to each of the pins of the IC under test MUT.
The main controller 100 is constituted by a computer system having its scale of, for example, a workstation or so, and a test program 101 created by a user (programmer) is previously stored therein, and the entire memory testing apparatus is controlled in accordance with the test program 101. The main controller 100 is connected to the timing generator TG, the pattern generator PG, and the like in the main frame 200 via a tester bus 201. A test for the memory under test MUT is carried out in accordance with control instructions/commands outputted from the main controller 100.
A pattern generating sequence described in the test program stored in the main controller 100 is previously stored in the pattern generator TG prior to the start of a test. When a test start instruction is given thereto from the main controller 100, the pattern generator PG outputs test pattern data to be applied to the memory under test MUT in accordance with the stored pattern generating sequence. As the pattern generator PG, an ALPG (Algorithmic Pattern Generator) is generally used. The ALPG is a pattern generator that generates a test pattern to be applied to a semiconductor device (for example, an IC) by an arithmetic and logic operation or computation using internal registers each having an arithmetic and logic function or computing function.
The timing generator TG has timing data previously stored therein prior to the start of a test, the timing data being described in the test program stored in the main controller 100 and outputted for every test period. The timing generator TG outputs a clock pulse (a timing pulse) for each test period in accordance with the stored timing data. This timing pulse is supplied to the waveform formatter FC, the logical comparator LOC and the like.
The waveform formatter FC defines a rise timing and a fall timing of a logical waveform, based on the test pattern data outputted from the pattern generator PG and the timing pulse outputted from the timing generator TG, to produce a test pattern signal having a real waveform that changes from/to logical H (logical xe2x80x9c1xe2x80x9d) to/from logical L (logical xe2x80x9c0xe2x80x9d). This test pattern signal is applied to the memory under test MUT via the drivers DR.
Each of the drivers DR defines the amplitude of the test pattern signal outputted from the waveform formatter FC to a desired amplitude (logical H, i.e., voltage of logical xe2x80x9c1xe2x80x9d and logical L, i.e., voltage of logical xe2x80x9c0xe2x80x9d) and applies such test pattern signal to the device socket of the test head 300, thereby to drive the memory under test MUT.
The voltage comparator VCP determines whether or not a logical value of a response signal outputted from the memory under test MUT has a normal voltage value. That is, the voltage comparator VCP determines whether or not a voltage of logical H has a value equal to or greater than a defined voltage value in case of the response signal of logical H and whether or not a voltage of logical L has a value equal to or less than a defined voltage value in case of the response signal of logical L.
In case the determination result of the voltage comparator VCP indicates a good result (pass), the output signal of the voltage comparator VCP is inputted to the logical comparator LOC where it is compared with an expected value pattern data (signal) EXP supplied from the pattern generator PG to determine whether or not the memory under test MUT has outputted a normal response signal. The comparison result of the logical comparator LOC is stored in the failure analysis memory AFM.
When the output signal of the voltage comparator VCP is not in accord with the expected value pattern data, the logical comparator LOC determines a memory cell of the memory under test MUT at the address thereof from which the response signal has been read out to be defective or failure, and generates a failure signal indicating that fact. Usually, when the failure signal is generated, a logical xe2x80x9c1xe2x80x9d signal being always applied to a data input terminal of the failure analysis memory AFM is enabled to be written in the failure analysis memory AFM, and the logical xe2x80x9c1xe2x80x9d data is written as a failure data in a memory cell of the failure analysis memory AFM specified by an address signal ADR supplied from the pattern generator PG. In general, a failure data (logical xe2x80x9c1xe2x80x9d) is stored in the same address of the failure analysis memory AFM as that of the failure memory cell of the memory under test MUT.
On the contrary, when the response signal of the memory under test is in accord with the expected value pattern data EXP, the logical comparator LOC determines a memory cell of the memory under test MUT at the address thereof from which the response signal has been read out to be normal, and generates a pass signal indicating that fact. Usually, the pass signal is not stored in the failure analysis memory AFM.
After the test has been completed, a failure analysis of the memory under test MUT is carried out with reference to the failure data stored in the failure analysis memory AFM. For example, in case the failure data are utilized for relief or repair of the failure memory cells, a failure map is created based on the read-out failure data whereby a decision is rendered as to whether or not the relief or repair of the failure memory cells is carried out.
As is well known, the failure analysis memory AFM is constructed by a memory having its storage capacity equal to or more than that of the memory under test MUT so that the failure determination results of all the bits of the memory under test MUT can be stored therein.
Accordingly, even in case of testing a flash memory, heretofore, the failure determination results of all the bits of the flash memory are also stored in the failure analysis memory AFM. After the test has been completed, each of the blocks of the flash memory is discriminated on the basis of an address signal supplied to the failure analysis memory AFM, and then the number of failure memory cells is counted for each block. Thereafter, for example, a failure relief analysis in which a decision is rendered whether the relief for the failure memory cells is possible or not, or the like is carried out.
In case of testing flash memories, an initial test for the flash memories is performed at first. Then, a functional test is performed only for the flash memories that have been determined to be pass articles. The initial test is carried out by way of example as follows: usually a logical value xe2x80x9c1xe2x80x9d (there may be a case of logical value xe2x80x9c0xe2x80x9d) is written in the memory cells of all the bits of a flash memory under test, and thereafter the written logical values are read out: When a read-out logical value is not in accord with the written logical value, that memory cell is determined to be defective, and a block containing such defective memory cell is determined to be a failure block.
There are many cases that a memory cell having the read-out logical value which has been not in accord with the written logical value in the initial test has a fatal defect and its relief is impossible. For this reason, in general, a block having at least one memory cell which has been determined to be defective in the initial test, namely, a failure block is regarded as an unusable block. If the number of failure blocks having been detected in the initial test is equal to or more than a predetermined number, for example, five or so, that flash memory under test has been determined to be a failure article at the stage of initial test, and any functional test for that flash memory is not performed.
The functional test is applied only to flash memories each having been determined to be a pass article in the initial test because it has less failure blocks than the prescribed value. In the functional test, the operation of writing a test pattern signal only in the blocks each of which has been determined to be pass block in the initial test (hereinafter referred to as pass block) and the operation of reading out the written test pattern signal therefrom are repeated, and the read-out data (that is, the response signal of the flash memory under test) is compared with the written data (that is, an expected value pattern data EXP from the pattern generator PG) in the logical comparator LOC to determine whether they are in accord with each other or not. In case both the data are not in accord with each other, a failure data of usually logical xe2x80x9c1xe2x80x9d is written, as mentioned above, in the same address of the failure analysis memory-AFM as that of the flash memory under test MUT at which the aforesaid disaccord has occurred to store therein the position of the memory cell where the disaccord has occurred. Then, after the functional test has been completed, the memory contents of the failure analysis memory AFM are read out therefrom to determine whether or not the relief or repair of the flash memory can be performed on the basis of the number of failure memory cells and the positions of failure memory cells.
As described above, in the test of a flash memory, a block having at least one defective memory cell detected in the initial test is determined to be a failure block, and the number of failure blocks is equal to or more than the predetermined number, that flash memory is determined to be a failure article. On the other hand, with respect to flash memories each having less failure blocks than the predetermined number, a functional test is applied only to the pass blocks of each of the flash memories. Consequently, the functional test is not applied to the failure blocks. Hereinafter, the failure block will be referred to as bad block.
For such reason, in the initial test, heretofore, an address area of the failure analysis memory AFM corresponding to each of the blocks of the flash memory under test is sequentially read one address by one address, whether or not data representing a failure (in general, data of logical xe2x80x9c1xe2x80x9d) is written in that address area is inspected, and based on this inspection result, whether or not the number of failures is equal to or greater than the prescribed value is determined. Accordingly, there is a drawback that it takes a long time to inspect failure data and the throughput of the test (efficiency of the test) is very poor.
Moreover, in the functional test for the flash memories subsequent to the initial test, unless the writing of data is correctly performed in each address of a pass block under test, a rewriting operation is repeated several times for each address of the subject pass block until the writing of data is correctly performed. When the number of the rewriting operations reaches a preset number of times, for example, six times or so, the writing of data in the current address is ceased and proceeds to the next address. At the same time, the address in which the writing of data could not have been done is stored in the failure analysis memory AFM as a failure address. Accordingly, there is a drawback that if there is an address in which the writing of data cannot be done at all in a pass block, the time duration required for carrying out the functional test becomes long because the time duration needed for the rewriting operations is added thereto.
Particularly, in case a plurality of flash memories are simultaneously tested, even if there exists only one flash memory that contains a failure address in a pass block, the writing operation for this flash memory is repeated a predetermined number of times when the failure address thereof is accessed. As a result, the remaining flash memories must await until the writing operation for the failure address is repetitively carried out predetermined number of times, notwithstanding that the writing operation for each of the remaining flash memories has been completed only once. Accordingly, there is a serious drawback that the remaining flash memories spend a waste of time, which results in longer test time.
In recent years, in order to reduce a testing cost, many semiconductor memory testing apparatus each being able to test and measure a multiplicity of (for example, 64) semiconductor memories at the same time have appeared, and when many flash memories are simultaneously tested by such a semiconductor memory testing apparatus, there is a strong possibility that at least one flash memory among them includes a failure address in its pass blocks. Accordingly, the aforesaid drawback resulting in longer test time eventually brings about an increase of the testing cost.
It is an object of the present invention to provide a memory testing apparatus which is capable of significantly reducing a time duration required for inspecting a bad block performed after the completion of the initial test for a non-volatile memory from which the stored data can be electrically erased in all bits en bloc or in block by block en bloc and in which data can be rewritten.
It is another object of the present invention to provide a memory testing apparatus which is capable of performing in a short time, in case of simultaneously testing a plurality of non-volatile memories from each of which the stored data can be electrically erased in all bits en bloc or in block by block en bloc and in each of which data can be rewritten, a functional test for pass blocks performed after the completion of the initial test.
It is further object of the present invention to provide a memory testing apparatus which is able to set therein various kinds of test modes.
In order to accomplish the above objects, in a first aspect of the present invention, there is provided a memory testing apparatus for testing a non-volatile memory from which the stored data can be electrically erased in all bits en bloc or in block by block en bloc and in which data can be rewritten, and comprising: a first bad block memory having its storage areas the number of which corresponds to the number of blocks that a memory under test has; and wherein in an initial test mode in which a constant logical value is written in memory cells of each of all the blocks of the memory under test, the written logical value is read out, a decision is rendered as to whether or not the read-out logical value is in accord with the written logical value, and a block having even one memory cell the read-out logical value from which is in disaccord with the written logical value is detected as a failure block, every time a failure block is detected, bad block data representing the failure block is stored in a storage area of the first bad block memory corresponding to the failure block.
In case of testing a plurality of memories under test at the same time, the aforesaid first bad block memory is provided one for each of the memories under test. In addition, the inside of the non-volatile memory is separated into a plurality of blocks, each of the blocks being constituted by N pages, and each of the N pages being constituted by M bits.
In a first preferred embodiment, the aforesaid memory testing apparatus further comprises block address selecting means for selecting a specified bit or bits from an address signal supplied to the memory under test to produce a block address signal for accessing a storage area of the first bad block memory corresponding to a block to which an address of the memory under test accessed by the address signal belongs.
The aforesaid block address selecting means selects, in a functional test mode, a specified bit or bits from an address signal included in a test pattern signal supplied to the memory under test to produce a block address signal for accessing a storage area of the first bad block memory, thereby to read out from the first bad block memory bad block data stored therein.
The aforesaid memory testing apparatus further comprises: mask control means for inhibiting, when bad block data is read out from the first bad block memory, a functional test for the memory under test from being carried out; and a bad block counter for counting the number of bad block data stored in the first bad block memory after the initial test has been completed.
In a second preferred embodiment, the aforesaid memory testing apparatus further comprises a second bad block memory for storing therein bad block data representing a failure block detected in a functional test mode, and the aforesaid bad block counter counts the number of bad block data stored in each of the first bad block memory and the second bad block memory after the initial test and the functional test have been completed.
With the construction described above, by reading out the storage contents of the first bad block memory, the number of bad blocks of a memory under test can be totalized in extremely short time. Accordingly, the time duration required for carrying out the initial test can significantly be reduced.
In addition, upon performing the functional test, a block address signal is produced from an address signal supplied to the memory under test, the first bad block memory is accessed by this block address signal to read out the storage contents of the first bad block memory, and a read-out bad block data is utilized as a mask data for stopping the functional test. Consequently, when a bad block data is read out, the functional test for a block of the memory under test corresponding to the block from which the bad block data is read out can immediately be inhibited from being performed. Accordingly, the time duration required for carrying out the functional test can be reduced.
Particularly, in case a plurality of memories under test are simultaneously tested, the functional test for a memory under test in which its bad block has been accessed is inhibited from being preformed, and hence the functional test for that bad block is not effected. As a result, it is not necessary to rewrite a test pattern signal repeatedly in the memory under test in which its bad block has been accessed. Accordingly, the remaining memories under test can immediately undergo the functional test without waiting until the lapse of a time duration required for repeatedly rewriting the test pattern signal in the memory under test in which its bad block has been accessed. Therefore, the time duration required for carrying out the functional test can greatly be reduced.